Phase-locked loops are widely used in digital electronics, signal telemetry, and communications applications. Phase-locked loop (PLL) integrated circuits produce an oscillator frequency output which matches an input frequency signal. Many applications require phase-locked loop (PLL) circuits which will work with high frequencies. Some such applications utilize PLL circuits which are reconfigurable. During a start-up process, high frequency PLL circuits may require indeterminate periods of time to achieve lock and initialize. Some high-frequency PLL circuits may fail to lock entirely. In particular, some high-frequency PLL circuits may have voltage-controlled oscillators (VCOs) with maximum output frequencies which approach or exceed maximum input frequencies of their respective dividers. Such high-frequency PLL circuits may have VCO output frequencies during start-up which are near or above the maximum input frequencies for their respective dividers. Thus, at start-up, some high-frequency PLL circuits may either lock after significant time and effort, or fail to lock entirely. Accordingly, a need exists for improved initialization for high-frequency PLL circuits. Further, a need exists for PLL circuits which may be configured to a steady state during initialization. It is desirable to improve PLL initialization without introducing noise to the PLL circuit.